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Adiabatic Logic Based Power Efficient Multiplexer

International Journal of Emerging Trends in Science and Technology

Volume 4 Issue 1

Published: 2018
Author(s) Name: P. Gomathi, P. Kaviya Priya, and Tha. Sugapriyaa | Author(s) Affiliation: Assistant Professor, Department of ECE, M. Kumarasamy College of Engineering, Tamil Nadu, India
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Abstract

This paper gives low power answers for VLSI. Power utilization of CMOS is quickly turning into a noteworthy worry in VLSI outline. Through adiabatic method dynamic power utilization in pull up system can be decreased and vitality put away on the heap capacitance can be reused. In this paper distinctive rationale style multiplexes have been dissected and low power 2:1 multiplexer is outlined utilizing positive criticism adiabatic rationale. It has been watched that adiabatic multiplexer devours 53.1% less power than vitality conserved pass-transistor (EEPL) multiplexer. An adiabatic compressor has been planned utilizing PFAL rationale, which has indicated 79% change than ordinary CMOS compressor as far as power. Every one of the reproductions are completed by Microwind 3.1 apparatus.

Keywords: CMOS, VLSI.

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