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Design and Optimization of FINFET Digital Circuits

International Journal of Research in Signal Processing, Computing & Communication System Design

Volume 2 Issue 1 & 2

Published: 2016
Author(s) Name: Pushpam Kolusu, K. Ragini | Author(s) Affiliation: ECE Department, GNITS, Hyderabad, Telangana, India
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Abstract

Over the last two decades, low-power design has become a concern in digital VLSI design, especially for portable and high performance systems. Large scale integration (LSI) has become so dense that a single silicon LSI chip may contain tens of thousands of transistors. Scaling of technology node increases power-density more than expected. CMOS technology beyond 65nm node represents a real challenge for any sort of voltage and frequency scaling Starting from 120nm node, each new process has inherently higher leakage current density with minimal improvement in speed. Low cost always continues to drive higher levels of integration, whereas low cost technological breakthroughs to keep power under control are getting very scarce. It is therefore necessary to look at other more revolutionary options like change in transistor structure from the traditional planar transistors. FINFET technology has been born as a result of increase in the levels of integration. Simulation is done in tanner tool in 45nm technology. Comparisions between CMOS and FINFET is clearly shown.

Keywords: CMOS, DGMOSFET, FINFET, Ion/Ioff, Low Power, Power Dissipation, Leakage Current

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