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Design of High Speed Standard Gate with Sub Threshold Dual Mode Logic using GPD45nm

International Journal of Research in Signal Processing, Computing & Communication System Design

Volume 1 Issue 2

Published: 2015
Author(s) Name: D.R.V.A. Sharath Kumar, J. Nageswara Reddy, A. Vamshidhar Reddy | Author(s) Affiliation:
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Abstract

Power applications. The supply voltage applied to the circuits operating in the sub-threshold region is equal to or less than the threshold voltages of the transistors, allowing a significant reduction of both dynamic and static power. The most common logic family used for sub-threshold operation is the Complementary Metal Oxide Semiconductor (CMOS). The dual mode logic based NAND, NOR and NOT gates are designed to operate in the sub threshold region. The proposed logic gates can be operated in two modes: static CMOS-like mode and dynamic CMOS-like mode. In the static mode of operation, the DML gates have very low power dissipation with moderate performance. When the DML gate is in the dynamic functional mode, they have much higher performance, at the cost of increased power dissipation. This particular feature of the Dual Mode Logic provides the option to control system performance on-the-fly and hence support applications in which a flexible workload is required.

Keywords: N.A.

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