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Implementation of Binary DAC and Two Step ADC Quantizer for CTDS using GPDK45nm

International Journal of Research in Signal Processing, Computing & Communication System Design

Volume 1 Issue 2

Published: 2015
Author(s) Name: D. R. V. A. Sharath Kumar, J. Nageswara Reddy, T. Swapna Rani | Author(s) Affiliation:
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Abstract

Two techniques to improve the performance of continuous-time delta–sigma (CTDS) modulators are presented. A digital calibration technique is introduced to enable the use of binary current digital-to-analog converters (DACs) without dynamic element matching. Furthermore, a high-speed two-step analog-to-digital data converter quantizer is introduced to efficiently increase the resolution of the quantizer in CTDS modulators with high-sampling rates. A proof-of-concept prototype implemented in 45-nm CMOS shows that the proposed calibration technique can compensate for up to 5% of mismatch in the DAC elements. The modulator has a measured SNDR/SFDR of 60.3/74 dB for a sampling rate of 350 MS/s and oversampling ratio of 20, translating to an 8.75-MHz bandwidth. The total power consumption is 5.5 mW from a 1.6 V supply.

Keywords: N.A.

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