2017 |
Volume 3 |
Issue Issue 1
Area Optimized and Frequency Efficient 1024 Point Radix-2 FFT Processor on FPGA
1.
Md. Ali Ghazi Islam
– M. E. Student, Eced, Muffakham Jah College Of Engineering And Tech., Hyderabad, Telangana, India.
2.
Kazi Nikhat Parvin
– M. E. Student, Eced, Muffakham Jah College Of Engineering And Tech., Hyderabad, Telangana, India.
3.
Md. Zakir Hussain
– M. E. Student, Eced, Muffakham Jah College Of Engineering And Tech., Hyderabad, Telangana, India.
Received
23-Aug-2017
|
Accepted
-
|
Published
23-Aug-2017
|
Abstract
This paper presents optimized area and frequency efficient Fast Fourier Transform (FFT) processor using radix-2 Decimation in Time (DIT) algorithm. The proposed FFT processor is a complex FFT processor where a time-multiplexed approach to the butterfly of 1024 point, fixed, 32-bit, based on Field Programmable Gate Array (FPGA) is designed. The architecture is based on burst I/O and the pipelined-streaming I/O structure in the butterfly module and the ping-pong operation which is clocking at 480 MHz on Xilinx vertex 6 xc6vlx550t-2ff1759.
Keywords Fast fourier transform, Field programmable gate array, Ping-pong operation, Pipelined-streaming I/O, Time-multiplexed butterfly.
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