1. – Dept. Of Electronics & Commun. Engg., Koneru Lakshmaiah Edun. Foundation (formerly K L Univ.), A.p.
| Received
20-Jul-2019 |
Accepted
- |
Published
20-Jul-2019 |
Abstract
This paper describes analysis and design of 2-stage CMOS operational amplifier (Op Amp). The designed circuit operates at 3.3 V of supply voltage and at tsmc 0.35 µm CMOS technology. The performance parameters such as: gain,
phase margin, GBW, ICMR, Slew Rate, Offset, CMRR, output swing etc. also have been analyzed after simulation which is carried out using Cadence Virtuoso Tool. The Op-Amp is designed to display a unity gain frequency of 7.85 MHz and exhibits a gain of 86.23 dB with a 49° phase margin. Obtained results also agree with theoretical predictions.
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